Video cameras and digital still cameras using a solid-state imaging device such as a Charge Coupled Device (CCD) are known. The development cycle for these cameras has been shortened and their costs also have decreased. Naturally, similar demands have been increased for components used in these cameras, and the reduction of the development cycle and the reduction of the cost for them are required.
A timing generator is an important component for generating a large number of timing pulses used for driving a solid-state imaging device. In order to realize an anti-shake function and an electronic zoom function of the cameras, a timing pulse complying with a vertical high-speed transfer mode of the solid-state imaging device is required.
JP S63(1988)-61560 A discloses a timing generator provided with a memory and a counter, in which the memory is for storing time-series data that represents a pattern of timing pulses and the counter is for sequentially assigning a readout address to this memory, which facilitates the change to specification.
JP H09(1997)-205591 A discloses a timing generator in which a timing pulse repeated in a horizontal direction and a timing pulse repeated in a vertical direction are obtained from separate memories, which is for the purpose of reducing memory capacity.
JP H10(1998)-257398 A discloses a timing generator provided with a decoder for decoding a rising pulse and a decoder for decoding a falling pulse, which allows a timing pulse to be configured with a program by means of a microcomputer.
JP 2002-51270 A discloses a timing generator that can reduce the amount of data to be stored in a built-in memory type timing generator that is for generating a timing pulse used for driving a solid-state imaging device and can realize a flexible function.
According to the timing generator described in JP 2002-51270 A, a large number of timing pulses having complicated waveforms that are used for driving the solid-state imaging device can be generated easily. However, after assembling it as an LSI for the timing generator, the pulse timing cannot be changed. Therefore, if the specification thereof needs to be changed, although the pulse timing can be changed easily, a separate LSI needs to be developed, thus posing a problem concerning the development cycle and the cost.